58 lines
2.2 KiB
Plaintext
58 lines
2.2 KiB
Plaintext
;; M Code
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;; option O0 O1 N1 O2 N2 O3 N3 O4 N4 O5 N5
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;; 4800 00 00 FF 00 FF 00 FF 00 FF 00 FF -- -- -- -- --
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;; 03D0|4810 -- -- -- -- -- -- -- -- -- -- -- -- 00 03 DF A6
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;; 03E0|4820 0D C7 52 32 C7 52 35 C7 52 31 5C 27 0D 72 0B 52
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;; 03F0|4830 30 F8 3B 52 31 5F 4C 26 F1 81 72 CC 48 3E 80 04
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;; UART1 register address definitions (STM8S103F3)
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UART1_SR = 0x5230 ; Status register
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UART1_DR = 0x5231 ; Data register
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UART1_BRR1 = 0x5232 ; Baud rate register 1
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UART1_CR2 = 0x5235 ; Control register 2
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RAM_SIZE = 0x0400 ; Ram size (end of address)
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;; Bootloader body (located in OPT reserved area 0x481C-0x483F)
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.area OPTION_BOOT
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_bootO_start_data:
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;; Termination flag (copy process stops when encountering 0)
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.db 0x00 ; [00] Termination byte
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;; [03 DF] RAM address for ret execution
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.db (RAM_SIZE-(_bootO_go_adr-_bootO_start+2))>>8
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.db (RAM_SIZE-(_bootO_go_adr-_bootO_start+2))&0xFF
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_bootO_start:
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;; Initialize UART 9600 8N1
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ld A, #0x0D ; [A6 0D] A = 0x0D (version number + UART configuration)
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ld UART1_BRR1, A ; [C7 52 32] Set baud rate
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ld UART1_CR2, A ; [C7 52 35] Enable UART transmit/receive
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;; Send BREAK signal and version number $0D
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ld UART1_DR, A ; [C7 52 31] Send version number 0x0D
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;; Receive maximum 243-byte data block and push onto stack
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_bootO_rx_byte:
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incw X ; [5C] Increment X, check for overflow (timeout detection)
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jreq _bootO_exit ; [27 0D] If X overflows (receive timeout), exit
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;; Wait for data reception
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btjf UART1_SR, #5, _bootO_rx_byte ;[72 0B 52 30 F8]
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;; Data received, push onto stack
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push UART1_DR ; [3B 52 31]
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clrw X ; [5F] Reset X (for timeout detection)
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inc A ; [4C] Increment A, used as receive counter
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jrne _bootO_rx_byte ; [26 F1] If A is not 0, continue receiving
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;; Reception complete, jump to received code
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ret ; [81] Jump to address at top of stack via ret instruction
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_bootO_exit:
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;; Timeout exit, jump to user program
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jp [_bootO_go_adr] ; [72 CC 48 3E] Indirect jump
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_bootO_go_adr:
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.db 0x80, 0x04 ; [80 04] User program address: 0x8004
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