diff --git a/Makefile b/Makefile
index 3b38442..f7f99a9 100644
--- a/Makefile
+++ b/Makefile
@@ -40,7 +40,8 @@ CFLAGS  += --stack-auto --noinduction --use-non-free
 ## Disable lospre (workaround for bug 2673)
 #CFLAGS  += --nolospre
 LDFLAGS  = -m$(ARCH) -l$(ARCH) --out-fmt-ihx
-BOOTFLAGS = -Wl-bOPTION=0x4800 -Wl-bOPTION_BOOT=0x480D -Wl-bRAM_BOOT=0x023E
+OPTFLAGS = -Wl-bOPTION=0x4800 -Wl-bOPTION_BOOT=0x480D
+B2FLAGS  = -Wl-bRAM_BOOT=0x023E
 
 # Conditionally add ENABLE_OPTION_BOOTLOADER macro
 ifneq ($(ENABLE_OPTION_BOOTLOADER),0)
@@ -112,7 +113,7 @@ endif
 
 # Link option bytes separately at address 0x4800
 $(BUILD_DIR)/option.hex: $(OPT_OBJS)
-	$(CC) $(LDFLAGS) $(BOOTFLAGS) $(OPT_OBJS) -o $@ || true
+	$(CC) $(LDFLAGS) $(OPTFLAGS) $(OPT_OBJS) -o $@
 
 $(BUILD_DIR)/option.bin: $(BUILD_DIR)/option.hex
 	$(OBJCOPY) -I ihex --output-target=binary $< $@
@@ -120,7 +121,7 @@ $(BUILD_DIR)/option.bin: $(BUILD_DIR)/option.hex
 boot2: $(SCRIPTS_DIR)/boot2.s | $(BUILD_DIR)
 	$(AS) $(ASFLAGS) $<
 	@mv $(SCRIPTS_DIR)/boot2.lst $(SCRIPTS_DIR)/boot2.rel $(SCRIPTS_DIR)/boot2.sym $(BUILD_DIR)/ 2>/dev/null || true
-	$(CC) $(LDFLAGS) $(BOOTFLAGS) $(BUILD_DIR)/boot2.rel -o $(BUILD_DIR)/boot2.hex || true
+	$(CC) $(LDFLAGS) $(B2FLAGS) $(BUILD_DIR)/boot2.rel -o $(BUILD_DIR)/boot2.hex
 	$(OBJCOPY) -I ihex --output-target=binary $(BUILD_DIR)/boot2.hex $(SCRIPTS_DIR)/boot2.bin
 
 # Show sizes of generated binaries
diff --git a/scripts/boot1.opt b/scripts/boot1.opt
index 28b60e0..49a684a 100644
--- a/scripts/boot1.opt
+++ b/scripts/boot1.opt
@@ -11,18 +11,19 @@ UART1_DR    = 0x5231   ; Data register
 UART1_BRR1  = 0x5232   ; Baud rate register 1
 UART1_CR2   = 0x5235   ; Control register 2
 
-RAM_SIZE    = 0x0400   ; Ram size (end of bootloader address)
+BOOT1_ULA   = 0x03FF   ; boot1 ram Upper-Limit-Address
 
-;; Bootloader body (located in OPT reserved area 0x481C-0x483F)
+;; Bootloader body (located in OPT reserved area 0x480D-0x483F)
+    .area   DATA
+    .area   HOME
     .area   OPTION_BOOT
 
-_boot_start_data:
     ;; Termination flag (copy process stops when encountering 0)
     .db     0x00       ; [00] Termination byte
 
     ;; [03 D0] RAM address for ret execution
-    .db     (RAM_SIZE-(_boot_go_adr-_boot_start+2))>>8
-    .db     (RAM_SIZE-(_boot_go_adr-_boot_start+2))&0xFF
+    .db     (BOOT1_ULA-(_boot_end-_boot_start)+1)>>8
+    .db     (BOOT1_ULA-(_boot_end-_boot_start)+1)&0xFF
 
 _boot_start:
     ;; Initialize UART 9600 8N1
@@ -70,3 +71,5 @@ _boot_exit:
 
 _boot_go_adr:
     .db     0x80, 0x04      ; [80 04] User program address: 0x8004
+
+_boot_end:
diff --git a/scripts/boot2.s b/scripts/boot2.s
index d0ba7d7..6c1d647 100644
--- a/scripts/boot2.s
+++ b/scripts/boot2.s
@@ -10,8 +10,6 @@
 ;   字节69: 校验和 (所有字节XOR)
 ; ================================================
 
-BOOT2_SP    = 0x03CD   ; start of boot1 ram address
-
 ;; Register address definitions
 UART1_SR    = 0x5230   ; Status register
 UART1_DR    = 0x5231   ; Data register
@@ -43,25 +41,29 @@ ERR_PGDIS    = 0xE3    ; 编程受保护的地址
 
 MAX_DATA_SIZE = 64     ; 最大数据长度
 
-;; Vars
-DEFAULT_SP_H = 0x0000  ; ram top address
-DEFAULT_SP_L = 0x0000  ; ram top address
-tx_buffer    = 0x0002  ; protocol tx buffer
-rx_buffer    = 0x0002  ; protocol rx buffer
-rx_state         = 72  ; 接收状态
-rx_length        = 73  ; 接收长度
-tx_state         = 74  ; 发送状态
-tx_data_length   = 75  ; 待发送的数据长度
-calc_checksum    = 76  ; 计算的校验和
-temp_var1        = 77  ; 临时变量
-temp_var2        = 78  ; 临时变量
-temp_var3        = 79  ; 临时变量
+;; Global vars
+;; After an MCU reset the Stack Pointer is set to its upper limit value
+DEFAULT_SP_H = 0x0000  ; Saved with SP value
+DEFAULT_SP_L = 0x0001  ;
+rx_state          = 2  ; 接收状态
+rx_length         = 3  ; 接收长度
+tx_state          = 4  ; 发送状态
+tx_data_length    = 5  ; 待发送的数据长度
+calc_checksum     = 6  ; 计算的校验和
+temp_var1         = 7  ; 临时变量
+temp_var2         = 8  ; 临时变量
+temp_var3         = 9  ; 临时变量
+tx_buffer    = 0x000A  ; protocol tx buffer
+rx_buffer    = 0x000A  ; protocol rx buffer
 
-;; Bootloader body (load in ram ?-0x03D0)
+BOOT2_ULA   = 0x03CF   ; boot2 ram Upper-Limit-Address
+
+    .area   DATA
+    .area   HOME
     .area   RAM_BOOT
 
-    .db     (BOOT2_SP-(_end-_start)+3)>>8
-    .db     (BOOT2_SP-(_end-_start)+3)&0xFF
+    .db     (BOOT2_ULA-(_end-_start)+1)>>8
+    .db     (BOOT2_ULA-(_end-_start)+1)&0xFF
 
 _start:
     ; 配置UART1: 128000波特率, 8N1, 启用TX/RX